Computer Science 432/563
Operating Systems

Spring 2016, The College of Saint Rose

Home     Syllabus     Schedule

Agenda

• Announcements
  • Term Project, continue work toward complete paper drafts.
  • Lab 7: Security continues
  • The take-home final exam will be distributed next Monday, due back next Wednesday
    • focus is on topics since the midterm, but likely to revisit process synchronization as well, and things you learned by doing the labs could come up
      • memory: paging, segmentation, virtual memory, etc
      • persistent storage and file systems
      • memory hierarchy including cache organization
      • protection and security, encryption
    • will not cover our architecture crash course topics from this week
    • open book, open notes, closed neighbors, closed Internet (other than specific course materials)
• Lecture 0x17 assignment recap
• The Protection and Security and Encryption topics will not be covered in class. Please read the notes. In particular, be sure you understand the basics of the public key encryption as described in the notes.
• Architecture crash course part 1: digital logic

Lecture 0x18 Assignment

Due at the start of class, Wednesday, April 27.

Please submit answers to these questions either as a hard copy (typeset or handwritten are OK) or by email to terescoj AT strose.edu by the start of class. Please use a clear subject line when submitting by email (e.g., CS 432 Lecture 0x18 Assignment, Mary Smith). We will discuss these questions at the start of class, so no late submissions are accepted.

The readings for next class are SG&G Chapter 14.

1. Explain briefly the security risk involved in having the entry "." in your search path in a Unix system. (3 points)
2. Since the time to access data for both hits and misses affects performance, designers often use an effective access time (EAT) to evaluate alternative cache designs. Effective access time can be defined as:
   EAT = t_hit + r_miss * t_miss
   for a hit time of t_hit, a miss rate of r_miss and a miss penalty of t_miss.
   a. Find the EAT for a processor with a 2 ns clock, t_miss = 20 clock cycles, r_miss = 0.05 misses per instruction, and a t_hit (cache access time, including hit detection) = 1 clock cycle. Assume that the read and write miss penalties are the same and ignore other write stalls. (4 points)
   b. Suppose we can improve r_miss to 0.03 misses per reference by doubling the cache size. This causes the cache access time t_hit to increase to 1.2 clock cycles. Using the EAT as a metric, determine if this is a good trade-off. (4 points)

Examples

See the Logisim example circuits in the shared areas on mogul and ascg.

Links

Topic notes links from an old offering of my computer organization class:

• Digital Logic