Fall 2010, Siena College

Lecture 18: Handling Hazards; Memory Hierarchy and Cache
Date: Tuesday, December 7, 2010

Agenda

• Announcements
• Happy CS Education Week!
• Please tear down your memory circuits and put away the components
• Lab 9 well underway now: due Monday at 4
• This week: we will meet to discuss other ISAs during lab meeting slots
• Final exam review: Friday, December 17, 1:30-3:30, RB 328 (here).
• Lecture assignment recap
• Augmenting pipeline data path and control to handle hazards
• Memory Hierarchy and Cache

Lecture Assignment 18

Due at the start of class, Thursday, December 9.

You need not submit answers to these questions, but you will have a chance to ask questions about them at the start of class.

P&H Exercise 5.4, all parts
Note: there is a mistake in the text's "Index" entry for the table in part b. The correct problem is below (11-5, not 11-15 as in the text).
For a direct-mapped cache design with 32-bit addresses, the following bits of the address are used to access the cache.
a. Tag: 31-10, Index: 9-4, Offset: 3-0
b. Tag: 31-12, Index: 11-5, Offset: 4-0
5.4.1. What is the cache line size (in words)?
5.4.2. How many entries does the cache have?
5.4.3. What is the ratio between total bits required for such a cache implementation over the data storage bits?
Starting from power on, the following byte-addresses cache references are recorded.

```0    = 0000 0000 0000
4    = 0000 0000 0100
16   = 0000 0001 0000
132  = 0000 1000 0100
232  = 0000 1110 1000
160  = 0000 1010 0000
1024 = 0010 0000 0000
30   = 0000 0001 1110
140  = 0000 1000 1100
3100 = 0110 0001 1100
180  = 0000 1011 0100
2810 = 1010 1111 1010
```

5.4.4. How many blocks are replaced?
5.4.5. What is the hit ratio?
5.4.6. List the final state of the cache, with each valid entry represented as a record of <index,tag,data>.