Computer Science 220
Assembly Language & Computer Architecture

Fall 2010, Siena College

Home     Syllabus     Schedule

Agenda

• Announcements
  • Lab 8 wrapping up this week
    • demo your circuits by Friday
    • anyone planning to work on them today?
  • Looking ahead: final exam review
  • Online course evaluations have begun
• Exam 2 back: optional meeting in RB 306 during regular lab sessions this week to go over the questions
• Much more on Lab 9
• Problems with the single cycle implementation
• Pipelining

Lecture Assignment 16

Due at the start of class, Thursday, December 2.

Please submit answers to these questions either as a hard copy (typeset or handwritten are OK) or by email to jteresco AT siena.edu by the start of class. We will discuss these questions at the start of class, so no late submissions are accepted. The textbook problem is reproduced here to aid those with a different version of the text.

P&H Exercise 4.12.1 and 4.12.2
In this exercise, we examine how pipelining affects the clock cycle time of the processor. Problems in this exercise assume that individual stages of the datapath have the following latencies:
a. IF: 300, ID: 400, EX: 350, MEM: 500, WB: 100
b. IF: 200, ID: 150, EX: 120, MEM: 190, WB: 140
4.12.1. What is the clock cycle time in a pipelined and nonpipelined processor?
4.12.2. What is the total latency of a lw instruction in a pipelined and nonpipelined processor?