Computer Science 324
Computer Architecture

Mount Holyoke College
Fall 2009


Lab 3: Memory with TTL
Due: 4:00 PM, Monday, October 19, 2009


Your task is to build, on a breadboard, the memory interface for a very small computer. You will use a number of readily available TTL components as building blocks.

We will make good use of our digital logic lab stations: our switches will represent 8 input lines from the "outside world" that can each carry a 0 or a 1, our 2 pushbuttons that produce the value 1 when pressed, 0 otherwise, will trigger the functionality of our circuit, and the 8 output lines that can be sampled for values will be connected to our LEDs. In a real computer, these input and output lines of our circuit would connect to other components instead of switches, pushbuttons, and LEDs.

Your implementation should include the following units:

Use the 74LSDataBook.pdf file to decide which chips you need. You should find appropriate chips in the lab. The memory chips can be found in an unmarked drawer in the bottom row in the chip storage unit.

When completed, the entire circuit should have the following capabilities and behaviors:

  1. Loading the MAR. When the A pushbutton is pressed, the value represented by the 8 data switches (SW7-SW0) is loaded into the MAR.
  2. Loading a value from "the outside world" (from the CPU in a real system) into the MBR. Data can be loaded into the MBR using the rightmost 4 data switches (SW3-SW0) by setting the leftmost 2 data switches (SW7 and SW6) low and pressing the B pushbutton. The other two switches are ignored.
  3. Storing the value in the MBR into memory. The data contained in the MBR can be stored into the memory location indicated by the MAR by setting SW7 to 1 and SW6 to 0 and pressing the B pushbutton.
  4. Retrieving a value from memory into the MBR. The data contained in memory at the address indicated by MAR can be stored in the MBR by setting SW7 to 1, SW6 to 1 and pressing the B pushbutton.

    You can think of SW7 as enabling a read/write between the MBR and memory (CS from our class discussions), with that SW6 controlling the direction of the data flow (RD/(not)WRT, or who's "driving" the data bus). Note: ensuring proper management of the data bus (i.e., at most one driver at a time) is one of the most important design decisions in this circuit.

  5. 4 outputs (LED3-LED0) should be configured to display the contents of the MBR at all times--even when the MBR is not driving the data bus. The other outputs (LED7-LED4) should be configured to display the contents of the data bus at all times.

A Logisim design or a hand-drawn circuit are not required, but would be accepted to increase your opportunity for partial credit should your circuit fail to work perfectly.

Your breadboard should be neat, with non-I/O (pin to pin) wires flat to the board. All chips and many of your wires should be labeled (use the small stickers you will find in the lab). This will not only aid in grading, but will be very helpful as you construct the circuit.

A correct circuit can be built using as few as 7 chips, but reasonable implementations may use a few more.

Be sure to design, implement, and test your circuit incrementally. Make sure each component is working as expected as you add it to your circuit. While all LEDs and switches have assigned purposes in the final circuit, you may wish to use them in other ways during the testing of your individual components.

You should plan to demonstrate your circuit before the due date. Circuits will be graded on correctness, good design, and neatness of wiring. Note: grades will not be recorded until you have taken down your circuit and neatly put away all wires and chips.