Computer Science 237
Computer Organization
Williams College
Fall 2005
Lecture 16: Latches and Flip-Flops
Date: October 17, 2005
Announcements
Lab 6 out: we will meet in TCL 216. We'll begin at 1:15, should be done by 2.
Agenda
latches: circuits that have two stable (remembered) states that may be selected by external control.
S-R latch; stores while high (or low)
NOR gate version (our preference)
Inverted logic NAND gate version (common)
S-R flip-flop (clocked latch/register) stores on
transition
Data flip-flops: D-type, commonly used in SRAM
latch/flip-flop distinction
Recall: SR-latch has
Q
and
Qbar
both low when
S=R=1
Note that the
AND
s gate or
strobe
the input to the S-R latch.
Note that
D
and
Dbar
are always opposite; they always attempt to change circuit.
J-K flip-flops
Attempts at avoiding badness (S=R=1)
Inhibits S or R if unnecessary.
Capable of other strange behavior if J=K=1; we'll harness this.
Toggling or T-type flip-flops
Counters
