Computer Science 237
Computer Organization

Williams College
Fall 2005

Lab 8: Memory with TTL
Due: Tuesday, November 8, 2005 at 2:30 PM (no late submissions)

We will meet briefly in the Digital Logic Lab in TCL 312b this week to get you started. Next week, you may demonstrate your circuits during either lab meeting time, or make other arrangements to demonstrate it before the end of Tuesday's lab period.

You are encouraged to work in groups of two for this lab.

This week's task is to build the memory interface for a very small computer.

Your implementation should include the following units, built with TTL logic on breadboards:

Use the 74LSDataBook.pdf file to decide which chips you need. You should find appropriate chips in the cabinet in TCL 312b. The memory chips can be found in the top unit of drawers, as can be some useful memory and tristate devices. You may also wish to use some of the logic gates we used previously.

When completed, the entire circuit should have the following capabilities and behaviors:

  1. Loading the MAR. When the "A" pushbutton is pressed, the value represented by the 8 data switches (SW7-SW0) is loaded into the MAR.
  2. Loading a value from "the outside world" (from the CPU in a real system) into the MBR. Data can be loaded into the MBR using the rightmost 4 data switches (SW3-SW0) by setting the leftmost 2 data switches (SW7 and SW6) low and pressing the "B" pushbutton. The other two switches are ignored.
  3. Storing the value in the MBR into memory. The data contained in the MBR can be stored into the memory location indicated by the MAR by setting SW7 to 1 and SW6 to 0 and pressing the "B" pushbutton.
  4. Retrieving a value from memory into the MBR. The data contained in memory at the address indicated by MAR can be stored in the MBR by setting SW7 to 1, SW6 to 1 and pressing the "B" pushbutton.

    You can think of SW7 as enabling a read/write between the MBR and memory (CS from our class discussions), with that SW6 controlling the direction of the data flow (RD/(not)WRT, or who's "driving" the data bus).

  5. The rightmost 4 LED's (LED3-LED0) should be configured to display the contents of the MBR at all times--even when the MBR is not driving the data bus. The leftmost 4 LED's (LED7-LED4) should be configured to display the contents of the data bus at all times.

You will have the chance during our regular lab meeting times to get started and to ask any logistical questions.

You are welcome to use LogicWorks to aid in your design. Your breadboard should, in the end, be neat with non-I/O wires flat to the board. Chips should be labeled (there are post-its in the cabinet).

Be sure to design, implement, and test your circuit incrementally. Make sure each component is working as expected as you add it to your circuit.

Depending on how many people choose to form groups, you may be allowed to keep a dedicated lab bench for your own use during the week. If not, you will need to share benches and swap out breadboards as needed. Please make sure that your bench is easily identifiable. You should plan to demonstrate your circuit no later than the end of lab period next Tuesday. Circuits will be graded on correctness, good design, and neatness of wiring.