Computer Science 220
Assembly Language & Computer Architecture

Fall 2011, Siena College

Lecture 0x1a: Memory Hierarchy and Cache
Date: Thursday, December 8, 2011


Lecture Assignment 0x1a

Due at the start of class, Never.

You need not submit answers to these questions, but you will have a chance to ask questions about them at the start of class.

  1. COD Exercise 5.4, all parts
  2. COD Exercise 5.6.4 and 5.6.5
  3. Since the time to access data for both hits and misses affects performance, designers often use an effective access time (EAT) to evaluate alternative cache designs. Effective access time can be defined as:
    EAT = thit + rmiss * tmiss
    for a hit time of thit, a miss rate of rmiss and a miss penalty of tmiss.
    a. Find the EAT for a processor with a 2 ns clock, tmiss = 20 clock cycles, rmiss = 0.05 misses per instruction, and a thit (cache access time, including hit detection) = 1 clock cycle. Assume that the read and write miss penalties are the same and ignore other write stalls.
    b. Suppose we can improve rmiss to 0.03 misses per reference by doubling the cache size. This causes the cache access time thit to increase to 1.2 clock cycles. Using the EAT as a metric, determine if this is a good trade-off.