Computer Science 237 Computer Organization Williams College Fall 2006

Agenda

• Announcements
  • Lab 6 continues
  • Next week: no formal lab meetings, one more assembly program
• Latches: circuits that have two stable (remembered) states that may be selected by external control
  • S-R latch; stores while high (or low)
    • NOR gate version (our preference)
    • Inverted logic NAND gate version (common)
  • S-R flip-flop (clocked latch/register) stores on transition
• Data flip-flops: D-type, commonly used in SRAM
• latch/flip-flop distinction
• Recall: SR-latch has Q and Qbar both low when S=R=1
  • Note that the ANDs gate or strobe the input to the S-R latch
  • Note that D and Dbar are always opposite; they always attempt to change circuit
• J-K Flip-Flops
  • Attempts at avoiding badness (S=R=1)
    • Inhibits S or R if unnecessary.
    • Capable of other strange behavior if J=K=1; we'll harness this.
• Toggling or T-type Flip-Flops
• Counters