Computer Science 237 Computer Organization Williams College Fall 2005

Announcements

• Microcode phase 1 due now. Now get started on phase 2!
• Everyone in class should have e-mailed me by now about their groups (or that they are going to be working alone).
• We're done with formal lab meetings, but I will be holding a session during normal lab times today and tomorrow to help people get their group permissions and source code control set up. You are encouraged to attend one of these sessions.

Agenda

• Microcode questions/answers
• The fetch-update-decode-execute loop
• RISC vs. CISC

  CISC or Complex Instruction Set Computer. Such computers:

  • Have instructions that are complex, for example, the string comparison instruction on the VAX, or the move multiple registers instruction on the 68000.

    Another example from the VAX: the SOBGTR instruction - subtract 1 and branch if the result is greater than 0. So an entire loop could be written:

            MOVAW   DATA,R6         ; load array ptr into R6
            MOVL    NUM,R9          ; initialize R9 with the number of elts
    DOUBLE: ADDW2   (R6),(R6)+      ; double entry, increment ptr
            SOBGTR  R9,DOUBLE       ; loop control
    

  • Have large instruction sets.
  • Support a large variety of addressing modes. The 68000 has a dozen or more operand modes.
  • Support for memory-based data in most instructions.
  • Are often microcoded.
  • Are heavily pipelined.
  • Relatively small numbers of registers. (a dozen or two)
  • Relatively compact code footprint.

  Researchers (many at Stanford) in the 1980's advocated for a RISC or reduced instruction set computer. Such computers:

  • Depend primarily on instructions that can be executed in one cycle.
  • The instruction sets may be large, but are easily decoded.
  • Support a small number of addressing modes.
  • Support explicit operations for memory access: LOAD and STORE. Such instructions may take multiple cycles, but might not delay the instruction stream.
  • Are simple enough for hardware-based decoding. (Some microcoding still there, likely)
  • Are pipelined, but pipes are shorter.
  • Larger number of registers, frequently supplanting the use of stack. (maybe thousands)
  • Relatively large code footprint.

  RISC details:

  • Simpler instruction formats: 3-operand operations, memory reference, conditional branch, jumps.
  • Frequently, small numbers of opcodes: (MIPS) 14 arithmetic, 4 load/store, 4 (×14) conditionals, 4 misc, 3 multiple cycle macro instructions. (SPARC) supports single step of multiply.
  • Typical pipeline (MIPS): instruction fetch, instruction decode, operand decode, execution, data write.
  • Rotating register file (SPARC): globals, ins, locals, and outs. Register window exposes a rotating subset of the file.
  • Instruction delays: load/store dependencies, delayed branching (static branch prediction), annulling (hints to branch predictor).
• Pipelines
• Register Windows

Examples

• assembly - compiler-generated assembly code for various processors