Computer Science 220
Assembly Language & Computer Architecture
Fall 2011, Siena College
Lecture 0x14: MIPS Single Cycle Implementation
Date: Tuesday, November 15, 2011
Agenda
- Announcements
- Exam 2 information and preparation
- All topics from transistors to error correcting memory
- Practice exam out Thursday
- We will go over all recent lab circuits in class on Thursday
- Q&A time in class next Tuesday
- Exam out at the end of class Tuesday, November 29, due back
at the start of class Thursday, December 1
- Lab 1000
- Circuit designs due at the start of your lab session
- Circuit demos due before you leave for Thanksgiving break,
but late penalty clock will not be running over the break
- Anyone individual wishing to be matched with a group or
group of 2 willing to take on a third member, please contact me
- Details of the ALU in our simple MIPS implementation
- The MIPS "Single Cycle" implementation
- Problems with the single cycle implementation
Lecture Assignment 0x14
Due at the start of class, Thursday, November 17.
Please submit answers to these questions
either as a hard copy (typeset or handwritten are OK) or by email to
jteresco AT siena.edu by the start of class. Please use a clear subject line
when submitting by email (e.g., CS 220 Lecture
Assignment 0x14, Joe Student). We will discuss these
questions at the start of class, so no late submissions are
accepted.
- P&H Exercise 4.1, p. 409 (Notes: In 4.1.1, consider all of the
labeled control signals in the figure, 4.1.5 should be the lw
instruction, not the LD instruction) (6 points)
- P&H Exercise 4.2.4 and 4.2.6, p. 411 (2 points)
- P&H Exercise 4.11.1, 4.11.2, 4.11.3, p. 419 (3 points)