Computer Science 220
Assembly Language & Computer Architecture

Fall 2010, Siena College

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Agenda

• Announcements
  • Please tear down remaining memory circuits right away
  • Lab 9 due Monday at 4
  • Friday lab meeting in RB 330 to discuss other ISAs (5 lab bonus points for being there!)
• Final exam information
  • practice exam out
  • focus on topics since last exam, but expect some small portion from previous (one question)
  • review: Friday, December 17, 1:30-3:30, RB 328 (here)
  • one double-sided page of handwritten notes permitted
• Cache memory
  • associativity
  • cache management
  • coherency issues

Practice Questions

Some questions to think about in preparation for the final.

1. P&H Exercise 5.6.4 and 5.6.5
   Cache block size (B) can affect both miss rate and miss latency. Assuming the following miss rate table, a 1-CPI machine with an average of 1.35 references (both instructions and data) per instruction, help find the optimal block size given the following miss rates for various block sizes:
   a. 8: 8%, 16: 3%, 32: 1.8%, 64: 1.5%, 128: 2%
   b. 8: 4%, 16: 4%, 32: 3%, 64: 1.5%, 128: 2%
   5.6.4. What is the optimal block size for a miss latency of 20 × B cycles?
   5.6.5. What is the optimal block size for a miss latency of 24 + B cycles?
2. Since the time to access data for both hits and misses affects performance, designers often use an effective access time (EAT) to evaluate alternative cache designs. Effective access time can be defined as:
   EAT = t_hit + r_miss * t_miss
   for a hit time of t_hit, a miss rate of r_miss and a miss penalty of t_miss.
   a. Find the EAT for a processor with a 2 ns clock, t_miss = 20 clock cycles, r_miss = 0.05 misses per instruction, and a t_hit (cache access time, including hit detection) = 1 clock cycle. Assume that the read and write miss penalties are the same and ignore other write stalls.
   b. Suppose we can improve r_miss to 0.03 misses per reference by doubling the cache size. This causes the cache access time t_hit to increase to 1.2 clock cycles. Using the EAT as a metric, determine if this is a good trade-off.

Links

• Cache Simulator from Edinburgh