Computer Science 220
Assembly Language & Computer Architecture

Fall 2010, Siena College

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Your task is to build, on a Proto-Board, the memory interface for a very small computer. You will use a number of readily available TTL components as building blocks.

We will make good use of our digital logic lab stations: our logic switches will represent 8 input lines from the "outside world" that can each carry a 0 or a 1, our 2 "debounced" pushbuttons that produce the value 1 when pressed, 0 otherwise, will trigger the functionality of our circuit, and the 8 output lines that can be sampled for values will be connected to our logic indicators. In a real computer, these input and output lines of our circuit would connect to other components instead of switches, pushbuttons, and logic indicators.

Due to equipment limitations, you will need to work in pairs again for this lab. You will work primarily in Roger Bacon 136, and may work on your circuits any time the lab is not being used for other purposes. If you would like to work on your circuit during the Tuesday, November 16 lab slot, it can be brought up to Roger Bacon 306 for the afternoon. You may store your Proto-Boards with your circuits on the shelf at the back of Roger Bacon 136 when you are not working on them. Be sure to label them with your names.

Circuit Components

Your implementation should include the following units:

• A 256 nibble memory. Use the 2114 1024×4 bit memory chips (leaving (3)/(4) of the nibbles unused). The 2114 is a memory device that has 10 address line inputs (A9, A8, ..., A0), 4 bidirectional data lines (D3, D2, D1, and D0), an active-low chip select (CS), and an active low write enable (WE). You can find out more about the 2114 in the file 74LSDataBook.pdf in the the course shared directory. Historical note: the 2114 was used to store high scores for some video game systems during the 1980's.
• The MAR (memory address register). This register drives the address bus unconditionally.
• The MBR (memory buffer register). This register reads values from and writes values to the data bus.

Use the 74LSDataBook.pdf file to decide which chips you need. You should find appropriate chips in the lab. The memory chips can be found in an unmarked drawer in the bottom row in the chip storage unit.

Circuit Functionality

When completed, the entire circuit should have the following capabilities and behaviors:

1. Loading the MAR. When the PB₁ pushbutton is pressed, the value represented by the 8 data switches (S₁-S₈) is loaded into the MAR.
2. Loading a value from "the outside world" (from the CPU in a real system) into the MBR. Data can be loaded into the MBR using the rightmost 4 data switches (S₅-S₈) by setting the leftmost 2 data switches (S₁ and S₂) low and pressing the PB₂ pushbutton. The other two switches are ignored.
3. Storing the value in the MBR into memory. The data contained in the MBR can be stored into the memory location indicated by the MAR by setting S₁ to 1 and S₂ to 0 and pressing the PB₂ pushbutton.
4. Retrieving a value from memory into the MBR. The data contained in memory at the address indicated by MAR can be stored in the MBR by setting S₁ to 1, S₂ to 1 and pressing the PB₂ pushbutton.

   You can think of S₁ as enabling a read/write between the MBR and memory (CS from our class discussions), with S₂ controlling the direction of the data flow (RD/(not)WRT, or who's "driving" the data bus). Note: ensuring proper management of the data bus (i.e., at most one driver at a time) is one of the most important design decisions in this circuit. While the 2114's data pins will drive their output only when the chip is enabled and reading, the switches and the chips you are likely to choose to construct your registers will always be driving their outputs. You will need tristate devices to ensure that their outputs are only placed on the data bus when needed (and when no one else is driving).

5. 4 outputs (LI1-LI4) should be configured to display the contents of the MBR at all times--even when the MBR is not driving the data bus. The other outputs (LI5-LI8) should be configured to display the contents of the data bus at all times.

Guidelines

A Logisim design or a hand-drawn circuit are not required, but would be accepted to increase your opportunity for partial credit should your circuit fail to work perfectly. The more complete your design before you begin wiring, the better your chances of a smooth wiring process and of a working circuit in the end.

Your breadboard should be neat, with non-I/O (pin to pin) wires as short as possible and flat to the board. All chips and many of your wires should be labeled (use the tape and small stickers you will find in the lab). This will not only aid in grading, but will be very helpful as you construct the circuit.

A correct circuit can be built using as few as 7 chips, but reasonable implementations may use a few more.

Be sure to design, implement, and test your circuit incrementally. Make sure each component is working as expected as you add it to your circuit. While all logic indicators and switches have assigned purposes in the final circuit, you may wish to use them in other ways during the testing of your individual components.

Grading and Evaluation

This lab is graded out of 40 points.

You should plan to demonstrate your circuit no later than 4:00 PM, Tuesday, November 23, 2010. Circuits will be graded mostly on correctness, but will also factor in good design, and neatness of wiring.

Note: grades will not be recorded until you have taken down your circuit and neatly put away all wires and chips.